The present invention relates to a data processing apparatus for processing data.
FIG. 9 shows part of a conventional data processing apparatus of this type. Referring to FIG. 9, reference numerals 1 to 4 denote latch circuits; and 5 and 6, gate circuits. Reference symbols PH1 and PH2 denote latch signals. In addition, a path1 indicated by the solid lines, a path2 indicated by the broken lines, and a path3 indicated by the alternate long and short dashed lines are transfer paths for data.
FIGS. 10A to 10F show the delayed states of data transferred on the respective transfer paths, i.e., the path1 to path3 and the timings of the latch signals PH1 and PH2 for latching the respective data. In this case, the latch signals PH1 and PH2 are output at timings A to C in synchronism with the clock signal shown in FIG. 10A.
In general, data transferred on the path1 to the path3 normally exhibit substantially uniform short transfer delays, as indicated by the timing A in FIGS. 10A to 10D, so that valid data can be obtained by the latch signal PH1 in FIG. 10E, which is synchronized with the clock signal in FIG. 10A, in a short period of time. Assume that an add operation is performed by a circuit connected to the path2, resulting in carry processing or the like. In this case, as indicated by the timing B in FIG. 10C, it takes a long period of time to output valid data. At this time, even if the latch signal PH2 shown in FIG. 10F is output to the latch circuit 4, the valid data on the path2 is not yet input to the latch circuit 4 through the gate circuits 5 and 6. Therefore, the latch circuit 4 cannot latch the valid data.
For this reason, in the conventional data processing apparatus, the output timing of the latch signal PH2, which is output in synchronism with the clock signal, is determined in consideration of the longest period of time required to validate data. In this case, since the time required to validate data is prolonged when the power supply voltage of the circuit is low or the ambient temperature is high, the output timing of the latch signal, i.e., the clock signal rate, is determined in consideration of such worst conditions as well.
In the conventional data processing apparatus, since the clock rate is determined in consideration of the longest period of time required to validate data, data is always loaded to be processed after this longest period of time even if the data is immediately validated. Therefore, the processing speed is unnecessarily suppressed to be low.